This invention relates in general to integrated circuits and, in particular, to a master-slice gate array integrated circuit device and method for fabricating the device.
In the semiconductor industry, a number of different design approaches have been used in the design and manufacture of integrated circuits. Two such approaches are custom logic and semi-custom logic. Custom logic typically requires expensive custom design to provide a made-to-order integrated circuit for specific functions. Even though custom integrated circuits are costly to design, they may be cost effective for large quantity production.
For devices which are to be produced in small or moderate quantities, semi-custom integrated circuits may be more cost effective. Semi-custom logic includes programmable array logic (PAL) where the "programming" is performed after the fabrication of the device has been completed, such as by blowing fuses using lasers. PAL type circuits, however, are typically limited in the number of gate counts that can be included. For integrated circuits requiring a large number of gates, master-slice gate array circuits are frequently used.
A typical conventional master-slice integrated circuit includes a core logic area surrounded by input/output border cells arranged along the periphery of the circuit. The core logic area ordinarily includes a matrix of basic cells. The input/output border cells often include transistors larger in size than the basic cells in the core logic so that these larger transistors may be used to construct input or output buffers that can provide a higher drive capability.
One conventional method for fabricating the above-described master-slice type integrated circuit is as follows. First, the diffusion regions of the basic cells and of the larger input/output transistor cells are defined and mask sets are designed for fabricating these diffusion regions as well as a polysilicon layer to form the gates of the transistors. A master-slice type integrated circuit so formed then can be used to construct desired logic circuits in accordance with customer specifications by interconnecting the basic cells and input/output cells using conductive interconnect layers composed of materials such as metal silicide or metal. The input/output cells are hereinafter simply referred to as "I/O cells." Thus, depending on the specific application intended by the user, different interconnections between the transistors of the core logic regions and the I/O border cells are made during later production. The complete circuit chip then is enclosed within a package.
The logic circuits requested by customers may include a wide range of different gate counts. To accommodate such a wide range of different gate counts, an application specific integrated circuit (ASIC) manufacturer would typically have to store an inventory of gate array architectures of different sizes, each of which has a respective capacity sufficient to accommodate up to some maximum number of gate cells. Thus, to efficiently map a completed circuit design into an integrated circuit architecture, the circuit designer would select, from an inventory of pre-established gate array die sizes (e.g., 1K, 2.5K, 5K, 7.5K, 10K and 20K gate cell arrays), the die size is selected such that it includes at least the number of gates required for a completed circuit design.
It should be noted that while reference to gates in a master slice array is common parlance, the more accurate characterization would be transistors in a master slice array. The transistors can be interconnected to form gates such as inverter gates or nano gates. However, prior to such interconnection, the array merely comprises a plurality of unconnected transistors which have not yet been connected to form gates.
Maintaining an inventory of fixed die sizes can be cumbersome and costly. First, the inventory requires significant manufacturing overhead, since each die size is in effect a custom architecture requiring its own dedicated mask set. Furthermore, because in certain array architectures the I/O cells are distributed around the periphery of the chip, the number of I/O cells that the die may contain is limited by the size of the die. Namely, circuit designs requiring a large number of I/O devices may be realized through the use of large sized die, while considerable portions of the core logic cell are of the large die may go unused. It is therefore desirable to provide a different master-slice type integrated circuit and system whereby the above-described disadvantages are avoided.
In U.S. Pat. No. 4,864,381 to Seefeldt et al., a variable die size gate array architecture is disclosed where, instead of placing the I/O cells at the periphery of the chip, such I/O cells are intermingled with the basic logic cells in the core logic area. The I/O cells differ from the basic logic cells in that each I/O cell includes a number of I/O driver circuits and associated terminal pads. A problem with the architecture disclosed by Seefeldt et at. is that, where a large number of I/O cells are not required for a customer's design, a significant portion of the chip area would remain unused. Since such I/O cells may include a number of I/O driver circuits and associated terminal pads, the percentage of unused chip area can be quite high, which is wasteful of resources. It is therefore desirable to provide an improved gate array architecture which does not include unnecessary I/O cells.
For master-slice gate arrays in CMOS technology, it is sometimes desirable for such gate arrays to provide surface space saving resistors. For example, resistors may be used in delay elements. Sometimes it is also desirable for the gate arrays to provide capacitors of a surface space saving design, for example, for constructing dynamic storage cells and delay elements. If the basic transistor cells in the core logic area are used to construct the capacitors and resistors, it may be necessary to use a relatively large number of the basic cells to provide resistors of high ohmic value and capacitors of high capacitance. It is therefore desirable to provide master-slice gate array circuits where such disadvantage is alleviated.
In U.S. Pat. No. 4,839,710 to Holzapfel et al., special cells are included in a gate array having long channel transistors which can be used to provide relatively large resistance and capacitance in the array. The special cells disclosed by Holzapfel et al., however, have channels which are bent or circuitous in shape and, therefore, occupy relatively larger regions. Such special cells require larger chip areas and can be somewhat difficult to produce using certain customary computer-aided design type techniques. There is a need for a basic cell which uses a long channel transistor that occupies relatively little space and is well suited to computer aided design techniques.